15 research outputs found
Predictive Barrier Lyapunov Function Based Control for Safe Trajectory Tracking of an Aerial Manipulator
This paper proposes a novel controller framework that provides trajectory
tracking for an Aerial Manipulator (AM) while ensuring the safe operation of
the system under unknown bounded disturbances. The AM considered here is a
2-DOF (degrees-of-freedom) manipulator rigidly attached to a UAV. Our proposed
controller structure follows the conventional inner loop PID control for
attitude dynamics and an outer loop controller for tracking a reference
trajectory. The outer loop control is based on the Model Predictive Control
(MPC) with constraints derived using the Barrier Lyapunov Function (BLF) for
the safe operation of the AM. BLF-based constraints are proposed for two
objectives, viz. 1) To avoid the AM from colliding with static obstacles like a
rectangular wall, and 2) To maintain the end effector of the manipulator within
the desired workspace. The proposed BLF ensures that the above-mentioned
objectives are satisfied even in the presence of unknown bounded disturbances.
The capabilities of the proposed controller are demonstrated through
high-fidelity non-linear simulations with parameters derived from a real
laboratory scale AM. We compare the performance of our controller with other
state-of-the-art MPC controllers for AM.Comment: European Control Conference '2
Flexible Spare Core Placement in Torus Topology based NoCs and its validation on an FPGA
In the nano-scale era, Network-on-Chip (NoC) interconnection paradigm has gained importance to abide by the communication challenges in Chip Multi-Processors (CMPs). With increased integration density on CMPs, NoC components namely cores, routers, and links are susceptible to failures.
Therefore, to improve system reliability, there is a need for efficient fault-tolerant techniques that mitigate
permanent faults in NoC based CMPs. There exists several fault-tolerant techniques that address the
permanent faults in application cores while placing the spare cores onto NoC topologies. However, these
techniques are limited to Mesh topology based NoCs. There are few approaches that have realized the
fault-tolerant solutions on an FPGA, but the study on architectural aspects of NoC is limited. This paper
presents the flexible placement of spare core onto Torus topology-based NoC design by considering core
faults and validating it on an FPGA. In the first phase, a mathematical formulation based on Integer Linear
Programming (ILP) and meta-heuristic based Particle Swarm Optimization (PSO) have been proposed for the
placement of spare core. In the second phase, we have implemented NoC router addressing scheme, routing
algorithm, run-time fault injection model, and fault-tolerant placement of spare core onto Torus topology
using an FPGA. Experiments have been done by taking different multimedia and synthetic application
benchmarks. This has been done in both static and dynamic simulation environments followed by hardware
implementation. In the static simulation environment, the experimentations are carried out by scaling the
network size and router faults in the network. The results obtained from our approach outperform the
methods such as Fault-tolerant Spare Core Mapping (FSCM), Simulated Annealing (SA), and Genetic
Algorithm (GA) proposed in the literature. For the experiments carried out by scaling the network size,
our proposed methodology shows an average improvement of 18.83%, 4.55%, 12.12% in communication
cost over the approaches FSCM, SA, and GA, respectively. For the experiments carried out by scaling the
router faults in the network, our approach shows an improvement of 34.27%, 26.26%, and 30.41% over the
approaches FSCM, SA, and GA, respectively. For the dynamic simulations, our approach shows an average
improvement of 5.67%, 0.44%, and 3.69%, over the approaches FSCM, SA, and GA, respectively. In the
hardware implementation, our approach shows an average improvement of 5.38%, 7.45%, 27.10% in terms
of application runtime over the approaches SA, GA, and FSCM, respectively. This shows the superiority of
the proposed approach over the approaches presented in the literature.publishedVersio
Fault-Tolerant Application-Specific Topology based NoC and its Prototype on an FPGA
Application-Specific Networks-on-Chips (ASNoCs) are suitable communication platforms for
meeting current application requirements. Interconnection links are the primary components involved in
communication between the cores of an ASNoC design. The integration density in ASNoC increases with
continuous scaling down of the transistor size. Excessive integration density in ASNoC can result in the
formation of thermal hotspots, which can cause a system to fail permanently. As a result, fault-tolerant
techniques are required to address the permanent faults in interconnection links of an ASNoC design.
By taking into account link faults in the topology, this paper introduces a fault-tolerant application-specific
topology-based NoC design and its prototype on an FPGA. To place spare links in the ASNoC topology,
a meta-heuristic algorithm based on Particle Swarm Optimization (PSO) is proposed. By taking link
faults into account in ASNoC design, we also propose an application mapping heuristic and a table-based
fault-tolerant routing algorithm. Experiments are carried out for a specific link and any link fault in
fault-tolerant topologies generated by our approach and approaches reported in the literature. For the experimentation, we used the multi-media applications Picture-in-Picture (PiP), Moving Pictures Expert Group
(MPEG) - 4, MP3Encoder, and Video Object Plane Decoder (VOPD). Experiments are run on software
and hardware platforms. The static performance metric communication cost and the dynamic performance
metrics network latency, throughput, and router power consumption are examined using software platform.
In the hardware platform, the Field Programmable Gate Array (FPGA) is used to validate proposed
fault-tolerant topologies and analyze performance metrics such as application runtime, resource utilization,
and power consumption. The results are compared with the existing approaches, specifically Ring topology
and its modified versions on both software and hardware platforms. The experimental results obtained from
software and hardware platforms for a specific link and any link fault show significant improvements in
performance metrics using our approach when compared with the related works in the literature.publishedVersio
Open Access Article│www.njcmindia.org pISSN 0976 3325│eISSN 2229 6816 National Journal of Community Medicine│Volume 4│Issue 3│July -Sept 2013 Kancheepuram District of Tamil Nadu, India and their Association with Risk Factors of Cardiovascular Diseases
ABSTRACT Background: The proportion of hypertension in India as reported by various literatures has been on an increasing trend for the last three decades. The present study was carried out to determine the proportion of hypertension, its associated risk factors as well as to increase the awareness on importance of life style modifications among people visiting a rural hospital
Flexible Spare Core Placement in Torus Topology based NoCs and its validation on an FPGA
In the nano-scale era, Network-on-Chip (NoC) interconnection paradigm has gained importance to abide by the communication challenges in Chip Multi-Processors (CMPs). With increased integration density on CMPs, NoC components namely cores, routers, and links are susceptible to failures.
Therefore, to improve system reliability, there is a need for efficient fault-tolerant techniques that mitigate
permanent faults in NoC based CMPs. There exists several fault-tolerant techniques that address the
permanent faults in application cores while placing the spare cores onto NoC topologies. However, these
techniques are limited to Mesh topology based NoCs. There are few approaches that have realized the
fault-tolerant solutions on an FPGA, but the study on architectural aspects of NoC is limited. This paper
presents the flexible placement of spare core onto Torus topology-based NoC design by considering core
faults and validating it on an FPGA. In the first phase, a mathematical formulation based on Integer Linear
Programming (ILP) and meta-heuristic based Particle Swarm Optimization (PSO) have been proposed for the
placement of spare core. In the second phase, we have implemented NoC router addressing scheme, routing
algorithm, run-time fault injection model, and fault-tolerant placement of spare core onto Torus topology
using an FPGA. Experiments have been done by taking different multimedia and synthetic application
benchmarks. This has been done in both static and dynamic simulation environments followed by hardware
implementation. In the static simulation environment, the experimentations are carried out by scaling the
network size and router faults in the network. The results obtained from our approach outperform the
methods such as Fault-tolerant Spare Core Mapping (FSCM), Simulated Annealing (SA), and Genetic
Algorithm (GA) proposed in the literature. For the experiments carried out by scaling the network size,
our proposed methodology shows an average improvement of 18.83%, 4.55%, 12.12% in communication
cost over the approaches FSCM, SA, and GA, respectively. For the experiments carried out by scaling the
router faults in the network, our approach shows an improvement of 34.27%, 26.26%, and 30.41% over the
approaches FSCM, SA, and GA, respectively. For the dynamic simulations, our approach shows an average
improvement of 5.67%, 0.44%, and 3.69%, over the approaches FSCM, SA, and GA, respectively. In the
hardware implementation, our approach shows an average improvement of 5.38%, 7.45%, 27.10% in terms
of application runtime over the approaches SA, GA, and FSCM, respectively. This shows the superiority of
the proposed approach over the approaches presented in the literature
Fault-Tolerant Application-Specific Topology based NoC and its Prototype on an FPGA
Application-Specific Networks-on-Chips (ASNoCs) are suitable communication platforms for
meeting current application requirements. Interconnection links are the primary components involved in
communication between the cores of an ASNoC design. The integration density in ASNoC increases with
continuous scaling down of the transistor size. Excessive integration density in ASNoC can result in the
formation of thermal hotspots, which can cause a system to fail permanently. As a result, fault-tolerant
techniques are required to address the permanent faults in interconnection links of an ASNoC design.
By taking into account link faults in the topology, this paper introduces a fault-tolerant application-specific
topology-based NoC design and its prototype on an FPGA. To place spare links in the ASNoC topology,
a meta-heuristic algorithm based on Particle Swarm Optimization (PSO) is proposed. By taking link
faults into account in ASNoC design, we also propose an application mapping heuristic and a table-based
fault-tolerant routing algorithm. Experiments are carried out for a specific link and any link fault in
fault-tolerant topologies generated by our approach and approaches reported in the literature. For the experimentation, we used the multi-media applications Picture-in-Picture (PiP), Moving Pictures Expert Group
(MPEG) - 4, MP3Encoder, and Video Object Plane Decoder (VOPD). Experiments are run on software
and hardware platforms. The static performance metric communication cost and the dynamic performance
metrics network latency, throughput, and router power consumption are examined using software platform.
In the hardware platform, the Field Programmable Gate Array (FPGA) is used to validate proposed
fault-tolerant topologies and analyze performance metrics such as application runtime, resource utilization,
and power consumption. The results are compared with the existing approaches, specifically Ring topology
and its modified versions on both software and hardware platforms. The experimental results obtained from
software and hardware platforms for a specific link and any link fault show significant improvements in
performance metrics using our approach when compared with the related works in the literature
Game Theory Explorer: software for the applied game theorist
his paper presents the “Game Theory Explorer” software tool to create and analyze games as models of strategic interaction. A game in extensive or strategic form is created and nicely displayed with a graphical user interface in a web browser. State-of-the-art algorithms then compute all Nash equilibria of the game after a mouseclick. In tutorial fashion, we present how the program is used, and the ideas behind its main algorithms. We report on experiences with the architecture of the software and its development as an open-source project